`timescale 1ns/100ps
/*************************************************************
 This file is for simulate AnonymousCore
**************************************************************/
module CoreSIM(

);
// GSR GSR_INST (.GSR (1'b1));
// PUR PUR_INST (.PUR (1'b1));
//----------------Global signals-----------------
    reg rstn;
	reg core_clk;
    reg clint_clk;

//----------------Core signal---------------------
    wire [07:0] byte_en;
	wire [63:0] Master_WB_ADRo;
	wire [63:0] Master_WB_DATi;
	wire [63:0] Master_WB_DATo;
	wire		Master_WB_WEo;
	wire		Master_WB_CYCo;
	wire		Master_WB_ACKi;
    wire RAM_WB_STBi,Console_WB_STBi;
//---------------------AnonymousCore-------------------------
    Core                            Core
    (
        .core_clk                   (core_clk),
        .clint_clk                  (clint_clk),
        .rstn                       (rstn), 
		.mei						(1'b0),
        .byte_en                    (byte_en),				
        .WB_ADRo                    (Master_WB_ADRo),
        .WB_DATo                    (Master_WB_DATo),
        .WB_DATi                    (Master_WB_DATi),
        .WB_WEo                     (Master_WB_WEo),
        .WB_CYCo                    (Master_WB_CYCo),
        .WB_ACKi                    (Master_WB_ACKi)
    );


    SimRAM								ram
    (
        .clk                        (core_clk),
        .rst                        (!rstn),
        .WB_WEi                     (Master_WB_WEo),
        .WB_CYCi                    (Master_WB_CYCo),
        .byte_en                    (byte_en),
        .WB_ADRi                    (Master_WB_ADRo),
        .WB_DATi                    (Master_WB_DATo),
        .WB_STBi                    (RAM_WB_STBi),
        .WB_ACKo                    (Master_WB_ACKi),
        .WB_DATo                    (Master_WB_DATi)
    );
    initial begin
        rstn	        =   1'b0;
	    core_clk	    = 	1'b0;	 
		clint_clk	    	= 	1'b0;

    #2000
        rstn            =   1'b1;
    end

    always begin
        #10 core_clk    =   ~ core_clk;	
		
    end	  
	always begin	
        #1000	clint_clk     =   ~ clint_clk;
    end

endmodule